MYIR’s $599 Vision Edge Computing Platform (VECP) Starter Kit uses Linux on the MYC-CZU3EG module based on Zynq UltraScale+ and includes a camera connected to Sony CSI and the vendor’s IP [email-protected] core, GigE Vision and USB3 Vision.
Last July, MYIR announced the MYC-CZU3EG processor module based on the Xilinx quad-A53, the Zynq UltraScale+ MPSoC assembled on FPGA and the MYD-CZU3EG development board. The company has now combined the module with a new MYD-CZU3EG-ISP card and a Sony IMX334LLR 8.42 megapixel camera to create a starter kit for the Vision Edge Computing Platform (VECP). The Linux-based suite supports video processing [secure email] for machine vision, industrial, IoT, and medical applications. Find out here now AWS Cloud management.
Vision Edge Computing Platform (VECP) Starter kit and image processing power with IP ISP and GiG-E cores and USB3 Vision
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The 60 x 52 mm MYC-CZU3EG module is installed as standard on the Zynq UltraScale+ XCZU3EG variant with a 667 MHz Mali 400 MP2 graphics processor. The VECP Starter Kit combines this model with the Linux stack, which is different from the module itself. You get Linux 4.14 with Boot.Bin, the gcc cross-compiler 7.2.1, the file system and much more, all with source code.
The MYC-CZU3EG processor features 4GB DDR4 flash memory, 4GB eMMC memory and 128MB QSPI memory, as well as GbE and USB PHY functions. The 3.3 V module with a temperature range from 0 to 70°C is equipped with a PMIC, watchdog timer, clock generator and 4x LEDs.
MYC-CZU3EG detail view (left) and available models Zynq UltraScale+ MPSoC
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Dual 0.5 mm pitch Samtec Express I/O connectors with 160 pins. The MYC-CZU3EG inputs/outputs connected to the FPGA include 156 PL I/O contacts for the user, 4x PS-GTR transceivers with 2 GTR reference generator inputs and 4x PL-GTH transceivers with 1 GTH and PS-MIO reference generator input.
PECV Starter Kit (MYD-CZU3EG-ISP)
The new MYD-CZU3EG-ISP card used in the VECP Starter Kit is 106.7 x 70 mm smaller than the MYD-CZU3EG media. Many functions are missing, including SATA, CAN, DisplayPort, LCD, PCIe, Arduino, PMod, FMC and an optional SFP optical network framework. However, it adds a second GbE port, an I/O expansion interface and a MIPI-CSI interface for the Sony rear view camera.
VECP starter kit MYD-CZU3EG-ISP board, front and rear
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The 8.42 megapixel Sony IMX334LLR (PDF) camera comes with an ISP core that can process video at a resolution of 3840 x 2160 at 30 frames per second and a very low latency video transmission at a maximum speed of 0.7 ms, according to MYIR. The camera has a pixel size of 2.0 μm × 2.0 μm with 12-bit ADC resolution and supports frame rates of up to 120 frames per second.
VECP starter kit with fan and block diagram
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The VECP Starter Kit supports Bayer, YCbCr and RGB video input formats and can output video via HDMI, USB 3.0 and GbE ports with FPGA connection. The card features a USB3 mink IP core and a GigE Vision IP core that supports GenICam V2.4.0 machine vision and custom XML.
The feature set of the MYD-CZU3EG-ISP includes USB 3.0 host and FPGA ports for USB devices, a micro-USB port for the serial console and two GbE ports, one for the armament unit and one for the FPGA.
MYD-CZU3EG-ISP Sample display
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Other features include a MicroSD slot, HDMI port, JTAG and fan connections and a start switch. The 12V/2A board has a 50-pin FPC I/I connector and can withstand temperatures from 0 to 70°C. The VECP starter kit includes HDMI and USB cables, power supply, fan, 16 GB microSD memory card and a documentation drive.
The VECP starter kit is available for $599, including the MYC-CZU3EG module. For more information please visit the MYIR Announcements and Products page.